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#Copyright (c) 2019 Intel Corporation
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xed_reg_enum_t XMM_B3()::
mode16 | OUTREG=XMM_B3_32()
mode32 | OUTREG=XMM_B3_32()
mode64 | OUTREG=XMM_B3_64()

xed_reg_enum_t XMM_B3_32()::
RM=0 | OUTREG=XED_REG_XMM0
RM=1 | OUTREG=XED_REG_XMM1
RM=2 | OUTREG=XED_REG_XMM2
RM=3 | OUTREG=XED_REG_XMM3
RM=4 | OUTREG=XED_REG_XMM4
RM=5 | OUTREG=XED_REG_XMM5
RM=6 | OUTREG=XED_REG_XMM6
RM=7 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7

REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15

REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31



xed_reg_enum_t YMM_B3()::
mode16 | OUTREG=YMM_B3_32()
mode32 | OUTREG=YMM_B3_32()
mode64 | OUTREG=YMM_B3_64()

xed_reg_enum_t YMM_B3_32()::
RM=0 | OUTREG=XED_REG_YMM0
RM=1 | OUTREG=XED_REG_YMM1
RM=2 | OUTREG=XED_REG_YMM2
RM=3 | OUTREG=XED_REG_YMM3
RM=4 | OUTREG=XED_REG_YMM4
RM=5 | OUTREG=XED_REG_YMM5
RM=6 | OUTREG=XED_REG_YMM6
RM=7 | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7
REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15

REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31



xed_reg_enum_t ZMM_B3()::
mode16 | OUTREG=ZMM_B3_32()
mode32 | OUTREG=ZMM_B3_32()
mode64 | OUTREG=ZMM_B3_64()

xed_reg_enum_t ZMM_B3_32()::
RM=0 | OUTREG=XED_REG_ZMM0
RM=1 | OUTREG=XED_REG_ZMM1
RM=2 | OUTREG=XED_REG_ZMM2
RM=3 | OUTREG=XED_REG_ZMM3
RM=4 | OUTREG=XED_REG_ZMM4
RM=5 | OUTREG=XED_REG_ZMM5
RM=6 | OUTREG=XED_REG_ZMM6
RM=7 | OUTREG=XED_REG_ZMM7

xed_reg_enum_t ZMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7
REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15
REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31