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#Copyright (c) 2019 Intel Corporation
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#  you may not use this file except in compliance with the License.
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#      http://www.apache.org/licenses/LICENSE-2.0
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xed_reg_enum_t XMM_N3()::
mode16 | OUTREG=XMM_N3_32()
mode32 | OUTREG=XMM_N3_32()
mode64 | OUTREG=XMM_N3_64()

xed_reg_enum_t XMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST210=0 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7

VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31


xed_reg_enum_t YMM_N3()::
mode16 | OUTREG=YMM_N3_32()
mode32 | OUTREG=YMM_N3_32()
mode64 | OUTREG=YMM_N3_64()

xed_reg_enum_t YMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST210=0 | OUTREG=XED_REG_YMM7


xed_reg_enum_t YMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31


xed_reg_enum_t ZMM_N3()::
mode16 | OUTREG=ZMM_N3_32()
mode32 | OUTREG=ZMM_N3_32()
mode64 | OUTREG=ZMM_N3_64()


xed_reg_enum_t ZMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_ZMM0
VEXDEST210=6 | OUTREG=XED_REG_ZMM1
VEXDEST210=5 | OUTREG=XED_REG_ZMM2
VEXDEST210=4 | OUTREG=XED_REG_ZMM3
VEXDEST210=3 | OUTREG=XED_REG_ZMM4
VEXDEST210=2 | OUTREG=XED_REG_ZMM5
VEXDEST210=1 | OUTREG=XED_REG_ZMM6
VEXDEST210=0 | OUTREG=XED_REG_ZMM7


xed_reg_enum_t ZMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31