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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING VPOPCNTB (VPOPCNTB-128-1)
{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
IFORM:       VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512
}

{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
IFORM:       VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPOPCNTB (VPOPCNTB-256-1)
{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
IFORM:       VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512
}

{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
IFORM:       VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPOPCNTB (VPOPCNTB-512-1)
{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
IFORM:       VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512
}

{
ICLASS:      VPOPCNTB
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
IFORM:       VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPOPCNTW (VPOPCNTW-128-1)
{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
IFORM:       VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512
}

{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
IFORM:       VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPOPCNTW (VPOPCNTW-256-1)
{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
IFORM:       VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512
}

{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
IFORM:       VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPOPCNTW (VPOPCNTW-512-1)
{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
IFORM:       VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512
}

{
ICLASS:      VPOPCNTW
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
IFORM:       VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1)
{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512
}

{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512
}


# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1)
{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512
}

{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512
}


# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1)
{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512
}

{
ICLASS:      VPSHUFBITQMB
CPL:         3
CATEGORY:    AVX512_BITALG
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BITALG_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8
IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512
}