#BEGIN_LEGAL
#
#Copyright (c) 2023 Intel Corporation
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#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
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#      http://www.apache.org/licenses/LICENSE-2.0
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#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
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#END_LEGAL
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#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
INSTRUCTIONS()::
# EMITTING ERETS (ERETS-N/A-1)
{
ICLASS:      ERETS
CPL:         0
CATEGORY:    FRED
EXTENSION:   FRED
ISA_SET:     FRED
REAL_OPCODE: Y
FLAGS:       MUST [  id-pop vip-pop vif-pop ac-pop vm-pop vm-pop rf-pop nt-pop nt-pop iopl-pop iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop  ]
ATTRIBUTES:  NOTSX 
PATTERN:    0x0F 0x01 MOD[0b11] MOD=3  REG[0b001] RM[0b010]  f2_refining_prefix      mode64 DF64()
OPERANDS:    REG0=XED_REG_STACKPOP:rw:SUPP:spw5 REG1=XED_REG_RIP:w:SUPP REG2=XED_REG_RFLAGS:w:SUPP:d:u32 REG3=XED_REG_RSP:w:SUPP:q:u64
IFORM:       ERETS
}


# EMITTING ERETU (ERETU-N/A-1)
{
ICLASS:      ERETU
CPL:         0
CATEGORY:    FRED
EXTENSION:   FRED
ISA_SET:     FRED
REAL_OPCODE: Y
FLAGS:       MUST [  id-pop vip-pop vif-pop ac-pop vm-pop vm-pop rf-pop nt-pop nt-pop iopl-pop iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop  ]
ATTRIBUTES:  NOTSX 
PATTERN:    0x0F 0x01 MOD[0b11] MOD=3  REG[0b001] RM[0b010]  f3_refining_prefix      mode64  DF64()
OPERANDS:    REG0=XED_REG_STACKPOP:rw:SUPP:spw5 REG1=XED_REG_CS:w:SUPP:u16 REG2=XED_REG_SS:w:SUPP:u16 REG3=XED_REG_RIP:w:SUPP REG4=XED_REG_RFLAGS:w:SUPP:d:u32 REG5=XED_REG_RSP:w:SUPP:q:u64 REG6=XED_REG_GSBASE:w:SUPP:u64 REG7=XED_REG_IA32_KERNEL_GS_BASE:w:SUPP:u64
IFORM:       ERETU
}


# EMITTING LKGS (LKGS-N/A-1)
{
ICLASS:      LKGS
CPL:         0
CATEGORY:    LKGS
EXTENSION:   LKGS
ISA_SET:     LKGS
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     0x0F 0x00 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix mode64
OPERANDS:    REG0=GPR16_B():r:w:u16 REG1=XED_REG_IA32_KERNEL_GS_BASE:w:SUPP:u64
IFORM:       LKGS_GPR16u16
}

{
ICLASS:      LKGS
CPL:         0
CATEGORY:    LKGS
EXTENSION:   LKGS
ISA_SET:     LKGS
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     0x0F 0x00 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() f2_refining_prefix mode64
OPERANDS:    MEM0:r:wrd:u16 REG0=XED_REG_IA32_KERNEL_GS_BASE:w:SUPP:u64
IFORM:       LKGS_MEMu16
}