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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1)
{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1)
{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1)
{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEINVQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1)
{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
IFORM:       VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1)
{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1)
{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VGF2P8AFFINEQB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
}


# EMITTING VGF2P8MULB (VGF2P8MULB-128-1)
{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
IFORM:       VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
}

{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
IFORM:       VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
}


# EMITTING VGF2P8MULB (VGF2P8MULB-256-1)
{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
IFORM:       VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
}

{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
IFORM:       VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
}


# EMITTING VGF2P8MULB (VGF2P8MULB-512-1)
{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
IFORM:       VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
}

{
ICLASS:      VGF2P8MULB
CPL:         3
CATEGORY:    GFNI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_GFNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
IFORM:       VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
}