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#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING VAESDEC (VAESDEC-128-1)
{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
IFORM:       VAESDEC_XMMu128_XMMu128_XMMu128_AVX512
}

{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
IFORM:       VAESDEC_XMMu128_XMMu128_MEMu128_AVX512
}


# EMITTING VAESDEC (VAESDEC-256-1)
{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
IFORM:       VAESDEC_YMMu128_YMMu128_YMMu128_AVX512
}

{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
IFORM:       VAESDEC_YMMu128_YMMu128_MEMu128_AVX512
}


# EMITTING VAESDEC (VAESDEC-512-1)
{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
IFORM:       VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512
}

{
ICLASS:      VAESDEC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
IFORM:       VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512
}


# EMITTING VAESDECLAST (VAESDECLAST-128-1)
{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
IFORM:       VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512
}

{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
IFORM:       VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512
}


# EMITTING VAESDECLAST (VAESDECLAST-256-1)
{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
IFORM:       VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512
}

{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
IFORM:       VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512
}


# EMITTING VAESDECLAST (VAESDECLAST-512-1)
{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
IFORM:       VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
}

{
ICLASS:      VAESDECLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
IFORM:       VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512
}


# EMITTING VAESENC (VAESENC-128-1)
{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
IFORM:       VAESENC_XMMu128_XMMu128_XMMu128_AVX512
}

{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
IFORM:       VAESENC_XMMu128_XMMu128_MEMu128_AVX512
}


# EMITTING VAESENC (VAESENC-256-1)
{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
IFORM:       VAESENC_YMMu128_YMMu128_YMMu128_AVX512
}

{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
IFORM:       VAESENC_YMMu128_YMMu128_MEMu128_AVX512
}


# EMITTING VAESENC (VAESENC-512-1)
{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
IFORM:       VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512
}

{
ICLASS:      VAESENC
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
IFORM:       VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512
}


# EMITTING VAESENCLAST (VAESENCLAST-128-1)
{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
IFORM:       VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512
}

{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
IFORM:       VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512
}


# EMITTING VAESENCLAST (VAESENCLAST-256-1)
{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
IFORM:       VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512
}

{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
IFORM:       VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512
}


# EMITTING VAESENCLAST (VAESENCLAST-512-1)
{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
IFORM:       VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
}

{
ICLASS:      VAESENCLAST
CPL:         3
CATEGORY:    VAES
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VAES_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
IFORM:       VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512
}


# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1)
{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b
IFORM:       VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512
}

{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
IFORM:       VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1)
{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512
}

{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
IFORM:       VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1)
{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPCLMULQDQ
CPL:         3
CATEGORY:    VPCLMULQDQ
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VPCLMULQDQ_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b
IFORM:       VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512
}