#BEGIN_LEGAL # #Copyright (c) 2020 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # #END_LEGAL AVX_INSTRUCTIONS():: { ICLASS : VPABSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 } { ICLASS : VPABSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 } { ICLASS : VPABSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 } { ICLASS : VPACKSSWB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPACKSSDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPACKUSWB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPACKUSDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPSLLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { ICLASS : VPSLLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 } { ICLASS : VPSLLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 } { ICLASS : VPSRLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { ICLASS : VPSRLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 } { ICLASS : VPSRLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 } { ICLASS : VPSRAW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 } { ICLASS : VPSRAD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 } { ICLASS : VPADDB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPADDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPADDD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPADDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 } { ICLASS : VPADDSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPADDSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPADDUSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPADDUSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPAVGB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPAVGW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPCMPEQB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPCMPEQW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPCMPEQD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPCMPEQQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 } { ICLASS : VPCMPGTB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPCMPGTW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPCMPGTD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPCMPGTQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 } { ICLASS : VPHADDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPHADDD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPHADDSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPHSUBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPHSUBD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPHSUBSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMADDWD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMADDUBSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPMAXSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPMAXSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMAXSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPMAXUB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPMAXUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPMAXUD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPMINSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPMINSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMINSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPMINUB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPMINUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPMINUD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPMULHUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPMULHRSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMULHW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMULLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPMULLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPMULUDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPMULDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPSADBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPSHUFB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPSIGNB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPSIGNW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPSIGND CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPSUBSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPSUBSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPSUBUSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPSUBUSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPSUBB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { ICLASS : VPSUBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { ICLASS : VPSUBD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { ICLASS : VPSUBQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 } { ICLASS : VPUNPCKHBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPUNPCKHWD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPUNPCKHDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPUNPCKHQDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 } { ICLASS : VPUNPCKLBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { ICLASS : VPUNPCKLWD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { ICLASS : VPUNPCKLDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPUNPCKLQDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 } { ICLASS : VPALIGNR CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b } { ICLASS : VPBLENDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b } { ICLASS : VMPSADBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b } { ICLASS : VPOR CPL : 3 CATEGORY : LOGICAL EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 } { ICLASS : VPAND CPL : 3 CATEGORY : LOGICAL EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 } { ICLASS : VPANDN CPL : 3 CATEGORY : LOGICAL EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 } { ICLASS : VPXOR CPL : 3 CATEGORY : LOGICAL EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 } { ICLASS : VPBLENDVB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 } { ICLASS : VPMOVMSKB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 } { ICLASS : VPSHUFD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b } { ICLASS : VPSHUFHW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b } { ICLASS : VPSHUFLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b } { ICLASS : VPSRLDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD } { ICLASS : VPSLLDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD } ############################################## { ICLASS : VPSLLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD } { ICLASS : VPSLLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD } { ICLASS : VPSLLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD } { ICLASS : VPSRAW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD } { ICLASS : VPSRAD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD } { ICLASS : VPSRLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD } { ICLASS : VPSRLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD } { ICLASS : VPSRLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-7 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD } ############################################################################ # SX versions ############################################################################ { ICLASS : VPMOVSXBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 } ############################################################################ { ICLASS : VPMOVSXBD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 } ############################################################################ { ICLASS : VPMOVSXBQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 } ############################################################################ { ICLASS : VPMOVSXWD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 } ############################################################################ { ICLASS : VPMOVSXWQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 } ############################################################################ { ICLASS : VPMOVSXDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 } ############################################################################ # ZX versions ############################################################################ { ICLASS : VPMOVZXBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 } ############################################################################ { ICLASS : VPMOVZXBD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 } ############################################################################ { ICLASS : VPMOVZXBQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 } ############################################################################ { ICLASS : VPMOVZXWD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 } ############################################################################ { ICLASS : VPMOVZXWQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 } ############################################################################ { ICLASS : VPMOVZXDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-5 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 } ################################## # newer stuff 2009-08-14 { ICLASS : VINSERTI128 CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b } { ICLASS : VEXTRACTI128 CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b } ########################################################################### ### # VPMASKMOVD masked load and store ### # VPMASKMOVQ masked load and store { ICLASS : VPMASKMOVD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 ATTRIBUTES: maskop EXCEPTIONS: avx-type-6 PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 } { ICLASS : VPMASKMOVQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 ATTRIBUTES: maskop EXCEPTIONS: avx-type-6 PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 } { ICLASS : VPMASKMOVD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 ATTRIBUTES: maskop EXCEPTIONS: avx-type-6 PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 } { ICLASS : VPMASKMOVQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 ATTRIBUTES: maskop EXCEPTIONS: avx-type-6 PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 } ########################################################################### ### # VPERM2I128 256b only { ICLASS : VPERM2I128 CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b } { ICLASS : VPERMQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b } { ICLASS : VPERMPD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b } { ICLASS : VPERMD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 PATTERN : VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { ICLASS : VPERMPS CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } ########################################################################### ### # VPBLENDD imm 128/256 { ICLASS : VPBLENDD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b } ########################################################################### { ICLASS : VPBROADCASTB COMMENT : gpr 128/256 CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 } { ICLASS : VPBROADCASTW COMMENT : gpr 128/256 CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 } ### # VPBROADCASTD gpr/mem { ICLASS : VPBROADCASTD COMMENT : gpr 128/256 CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 } ### # VPBROADCASTQ gpr/mem { ICLASS : VPBROADCASTQ COMMENT : gpr 128/256 CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 } { ICLASS : VBROADCASTSS CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 COMMENT : xmm,xmm and ymm,xmm PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 } { ICLASS : VBROADCASTSD CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 COMMENT : ymm,xmm only PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 } { ICLASS : VBROADCASTI128 CPL : 3 CATEGORY : BROADCAST EXTENSION : AVX2 EXCEPTIONS: avx-type-6 COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 }