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#Copyright (c) 2019 Intel Corporation
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# SPARSE OPERATIONS REQUIRE A SPECIAL MODRM BYTE and a mandatory VSIB BYTE

VMODRM_YMM()::
 MOD=0b00  VSIB_YMM()             | 
 MOD=0b01  VSIB_YMM() MEMDISP8()  | 
 MOD=0b10  VSIB_YMM() MEMDISP32() | 


VMODRM_XMM()::
 MOD=0b00  VSIB_XMM()             | 
 MOD=0b01  VSIB_XMM() MEMDISP8()  | 
 MOD=0b10  VSIB_XMM() MEMDISP32() | 

VSIB_YMM()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_YMM()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_YMM()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_YMM()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_YMM()  SCALE=8  

VSIB_XMM()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_XMM()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_XMM()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_XMM()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE()  | INDEX=VSIB_INDEX_XMM()  SCALE=8  

xed_reg_enum_t VSIB_INDEX_YMM()::
REXX=0   SIBINDEX=0 | OUTREG=XED_REG_YMM0
REXX=0   SIBINDEX=1 | OUTREG=XED_REG_YMM1
REXX=0   SIBINDEX=2 | OUTREG=XED_REG_YMM2
REXX=0   SIBINDEX=3 | OUTREG=XED_REG_YMM3
REXX=0   SIBINDEX=4 | OUTREG=XED_REG_YMM4
REXX=0   SIBINDEX=5 | OUTREG=XED_REG_YMM5
REXX=0   SIBINDEX=6 | OUTREG=XED_REG_YMM6
REXX=0   SIBINDEX=7 | OUTREG=XED_REG_YMM7
REXX=1   SIBINDEX=0 | OUTREG=XED_REG_YMM8
REXX=1   SIBINDEX=1 | OUTREG=XED_REG_YMM9
REXX=1   SIBINDEX=2 | OUTREG=XED_REG_YMM10
REXX=1   SIBINDEX=3 | OUTREG=XED_REG_YMM11
REXX=1   SIBINDEX=4 | OUTREG=XED_REG_YMM12
REXX=1   SIBINDEX=5 | OUTREG=XED_REG_YMM13
REXX=1   SIBINDEX=6 | OUTREG=XED_REG_YMM14
REXX=1   SIBINDEX=7 | OUTREG=XED_REG_YMM15


xed_reg_enum_t VSIB_INDEX_XMM()::
REXX=0   SIBINDEX=0 | OUTREG=XED_REG_XMM0
REXX=0   SIBINDEX=1 | OUTREG=XED_REG_XMM1
REXX=0   SIBINDEX=2 | OUTREG=XED_REG_XMM2
REXX=0   SIBINDEX=3 | OUTREG=XED_REG_XMM3
REXX=0   SIBINDEX=4 | OUTREG=XED_REG_XMM4
REXX=0   SIBINDEX=5 | OUTREG=XED_REG_XMM5
REXX=0   SIBINDEX=6 | OUTREG=XED_REG_XMM6
REXX=0   SIBINDEX=7 | OUTREG=XED_REG_XMM7
REXX=1   SIBINDEX=0 | OUTREG=XED_REG_XMM8
REXX=1   SIBINDEX=1 | OUTREG=XED_REG_XMM9
REXX=1   SIBINDEX=2 | OUTREG=XED_REG_XMM10
REXX=1   SIBINDEX=3 | OUTREG=XED_REG_XMM11
REXX=1   SIBINDEX=4 | OUTREG=XED_REG_XMM12
REXX=1   SIBINDEX=5 | OUTREG=XED_REG_XMM13
REXX=1   SIBINDEX=6 | OUTREG=XED_REG_XMM14
REXX=1   SIBINDEX=7 | OUTREG=XED_REG_XMM15


VSIB_BASE()::
REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()

REXB=0 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=0 SIBBASE=5 MOD!=0             | BASE0=ArBP() SEG0=FINAL_SSEG()

REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()

REXB=1 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()

REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()