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#Copyright (c) 2023 Intel Corporation
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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
AVX_INSTRUCTIONS()::
# EMITTING VSM3MSG1 (VSM3MSG1-128-1)
{
ICLASS:      VSM3MSG1
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDA VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
IFORM:       VSM3MSG1_XMMu32_XMMu32_XMMu32
}

{
ICLASS:      VSM3MSG1
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDA VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
IFORM:       VSM3MSG1_XMMu32_XMMu32_MEMu32
}


# EMITTING VSM3MSG2 (VSM3MSG2-128-1)
{
ICLASS:      VSM3MSG2
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDA V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
IFORM:       VSM3MSG2_XMMu32_XMMu32_XMMu32
}

{
ICLASS:      VSM3MSG2
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
IFORM:       VSM3MSG2_XMMu32_XMMu32_MEMu32
}


# EMITTING VSM3RNDS2 (VSM3RNDS2-128-1)
{
ICLASS:      VSM3RNDS2
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b
IFORM:       VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8
}

{
ICLASS:      VSM3RNDS2
CPL:         3
CATEGORY:    VEX
EXTENSION:   SM3
ISA_SET:     SM3
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xDE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b
IFORM:       VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8
}