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EVEX_INSTRUCTIONS()::
# EMITTING VPDPBUSD (VPDPBUSD-128-1)
{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
IFORM:       VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
}

{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
}


# EMITTING VPDPBUSD (VPDPBUSD-256-1)
{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
IFORM:       VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
}

{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
}


# EMITTING VPDPBUSD (VPDPBUSD-512-1)
{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
IFORM:       VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
}

{
ICLASS:      VPDPBUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
}


# EMITTING VPDPBUSDS (VPDPBUSDS-128-1)
{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
IFORM:       VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
}

{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
}


# EMITTING VPDPBUSDS (VPDPBUSDS-256-1)
{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
IFORM:       VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
}

{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
}


# EMITTING VPDPBUSDS (VPDPBUSDS-512-1)
{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
IFORM:       VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
}

{
ICLASS:      VPDPBUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
}


# EMITTING VPDPWSSD (VPDPWSSD-128-1)
{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
IFORM:       VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
}

{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
}


# EMITTING VPDPWSSD (VPDPWSSD-256-1)
{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
IFORM:       VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
}

{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
}


# EMITTING VPDPWSSD (VPDPWSSD-512-1)
{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
IFORM:       VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
}

{
ICLASS:      VPDPWSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
}


# EMITTING VPDPWSSDS (VPDPWSSDS-128-1)
{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
IFORM:       VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
}

{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
}


# EMITTING VPDPWSSDS (VPDPWSSDS-256-1)
{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
IFORM:       VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
}

{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
}


# EMITTING VPDPWSSDS (VPDPWSSDS-512-1)
{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
IFORM:       VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
}

{
ICLASS:      VPDPWSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
}