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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
EVEX_INSTRUCTIONS()::
# EMITTING VP2INTERSECTD (VP2INTERSECTD-128-1)
{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
IFORM:       VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512
}


# EMITTING VP2INTERSECTD (VP2INTERSECTD-256-1)
{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
IFORM:       VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512
}


# EMITTING VP2INTERSECTD (VP2INTERSECTD-512-1)
{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32
IFORM:       VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VP2INTERSECTD
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-128-1)
{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64
IFORM:       VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512
}


# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-256-1)
{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64
IFORM:       VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512
}

{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512
}


# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-512-1)
{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 MASK=0 
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64
IFORM:       VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VP2INTERSECTQ
CPL:         3
CATEGORY:    AVX512_VP2INTERSECT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VP2INTERSECT_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULL MULTIDEST2 BROADCAST_ENABLED 
PATTERN:    EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512
}