#BEGIN_LEGAL # #Copyright (c) 2023 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # #END_LEGAL ########################################################################### ## file: xed-addressing-modes-new.txt ########################################################################### # inputs: # REX = REX or NOREX # REXB = REXB0 or REXB1 # REXB4 = REXB4=0 or REXB4=1 # REXX = REXX0 or REXX1 # REXX4 = REXX4=0 or REXX4=1 # MODE = MODE32 or MODE64 # outputs: # SEG0, BASE0, INDEX, SCALE, DISP and # a register id to be evaluated at a higher level # The 32b and 64b share SIB/SIB_BASE0 productions. The registers there # have to be converted to the right width. Similarly, the rAX'es etc # in the MODRM64alt32 need to be scaled by ASZ. So rAX is either RAX # or EAX and r15 is either R15 or R15D depending on ASZ. # Sooo. for the BASE0/SIB_BASE0,INDEX, we need a lookup like: # base_or_index_reg_lookup(rex,rexb/x,RM,mode,asz) # The ASZ operand will do different things. In 32b mode it is not used # because the ASZ would take use to 16 mode addressing. In 64b mode, # it tells use to use 64 or 32b registers. ############################################################################ MODRM():: # # NOTE: the RIP handling in 64b mode with effective addressing of 32b # is different than the 32b addressing in 32b mode when MODRM.MOD=00_ # and MODRM.RM=101, where it is just #a base, not RIP relative. # mode64 eamode64 MODRM64alt32() MEMDISP() | mode64 eamode32 MODRM64alt32() MEMDISP() | mode32 eamode32 MODRM32() MEMDISP() | mode32 eamode16 MODRM16() MEMDISP() | mode16 eamode32 MODRM32() MEMDISP() | mode16 eamode16 MODRM16() MEMDISP() | ############################################################################ MODRM64alt32():: REXB4=0 REXB=0 MOD=0b00 RM=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b000 | BASE0=Ar16() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b000 | BASE0=Ar24() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b00 RM=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b001 | BASE0=Ar17() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b001 | BASE0=Ar25() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b00 RM=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b010 | BASE0=Ar18() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b010 | BASE0=Ar26() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b00 RM=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b011 | BASE0=Ar19() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b011 | BASE0=Ar27() SEG0=FINAL_DSEG() # Ignores rexb and rexb4 -- must duplicate to avoid don't-care problems REXB4=0 REXB=0 MOD=0b00 RM=0b100 SIB() | REXB4=0 REXB=1 MOD=0b00 RM=0b100 SIB() | REXB4=1 REXB=0 MOD=0b00 RM=0b100 SIB() | REXB4=1 REXB=1 MOD=0b00 RM=0b100 SIB() | # Ignores rexb and rexb4 -- must duplicate to avoid don't-care problems REXB4=0 REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() enc REXB4=0 REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() enc REXB4=1 REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b00 RM=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b110 | BASE0=Ar22() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar30() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b00 RM=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b00 RM=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b00 RM=0b111 | BASE0=Ar23() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b00 RM=0b111 | BASE0=Ar31() SEG0=FINAL_DSEG() ############################################ REXB4=0 REXB=0 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=ArAX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar8() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar16() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar24() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=ArCX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar9() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar17() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar25() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=ArDX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar10() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar18() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar26() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=ArBX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar11() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar19() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar27() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 REXB4=0 REXB=1 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 REXB4=1 REXB=0 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 REXB4=1 REXB=1 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 REXB4=0 REXB=0 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=ArBP() SEG0=FINAL_SSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar13() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar21() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar29() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=ArSI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar14() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar22() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar30() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=ArDI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar15() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar23() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar31() SEG0=FINAL_DSEG() ############################################ REXB4=0 REXB=0 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=ArAX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar8() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar16() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar24() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=ArCX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar9() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar17() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar25() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=ArDX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar10() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar18() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar26() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=ArBX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar11() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar19() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar27() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 REXB4=0 REXB=1 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 REXB4=1 REXB=0 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 REXB4=1 REXB=1 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 REXB4=0 REXB=0 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=ArBP() SEG0=FINAL_SSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar13() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar21() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar29() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=ArSI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar14() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar22() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar30() SEG0=FINAL_DSEG() REXB4=0 REXB=0 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=ArDI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar15() SEG0=FINAL_DSEG() REXB4=1 REXB=0 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar23() SEG0=FINAL_DSEG() REXB4=1 REXB=1 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar31() SEG0=FINAL_DSEG() ############################################ MODRM32():: MOD=0b00 RM=0b000 | BASE0=XED_REG_EAX SEG0=FINAL_DSEG() MOD=0b00 RM=0b001 | BASE0=XED_REG_ECX SEG0=FINAL_DSEG() MOD=0b00 RM=0b010 | BASE0=XED_REG_EDX SEG0=FINAL_DSEG() MOD=0b00 RM=0b011 | BASE0=XED_REG_EBX SEG0=FINAL_DSEG() MOD=0b00 RM=0b100 SIB() | MOD=0b00 RM=0b101 | NEED_MEMDISP=32 SEG0=FINAL_DSEG() MOD=0b00 RM=0b110 | BASE0=XED_REG_ESI SEG0=FINAL_DSEG() MOD=0b00 RM=0b111 | BASE0=XED_REG_EDI SEG0=FINAL_DSEG() #################################### MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() #################################### MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() ############################################ ################################################### # 16 bit addressing MODRM bytes MODRM16():: MOD=0b00 RM=0b000 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b00 RM=0b001 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b00 RM=0b010 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b00 RM=0b011 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b00 RM=0b100 | BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b00 RM=0b101 | BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b00 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b00 RM=0b111 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID ############################################# MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b01 RM=0b100 | NEED_MEMDISP=8 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID ############################################# MOD=0b10 RM=0b000 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 MOD=0b10 RM=0b100 | NEED_MEMDISP=16 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b10 RM=0b101 | NEED_MEMDISP=16 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID MOD=0b10 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID MOD=0b10 RM=0b111 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID ############################################ SIB():: # SCALE = 1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar16() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar24() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar17() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar25() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar18() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar26() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar19() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar27() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 enc REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar20() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar28() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar21() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar29() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar22() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar30() SCALE=1 REXX4=0 REXX=0 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=1 REXX4=1 REXX=0 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar23() SCALE=1 REXX4=1 REXX=1 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar31() SCALE=1 # SCALE = 2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar16() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar24() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar17() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar25() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar18() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar26() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar19() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar27() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar20() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar28() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar21() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar29() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar22() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar30() SCALE=2 REXX4=0 REXX=0 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=2 REXX4=0 REXX=1 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=2 REXX4=1 REXX=0 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar23() SCALE=2 REXX4=1 REXX=1 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar31() SCALE=2 # SCALE = 4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar16() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar24() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar17() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar25() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar18() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar26() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar19() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar27() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar20() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar28() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar21() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar29() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar22() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar30() SCALE=4 REXX4=0 REXX=0 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=4 REXX4=0 REXX=1 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=4 REXX4=1 REXX=0 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar23() SCALE=4 REXX4=1 REXX=1 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar31() SCALE=4 # SCALE = 8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar16() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar24() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar17() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar25() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar18() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar26() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar19() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar27() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar20() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar28() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar21() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar29() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar22() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar30() SCALE=8 REXX4=0 REXX=0 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=8 REXX4=0 REXX=1 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=8 REXX4=1 REXX=0 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar23() SCALE=8 REXX4=1 REXX=1 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar31() SCALE=8 ################################################### SIB_BASE0():: REXB4=0 REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b000 | BASE0=Ar16() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b000 | BASE0=Ar24() SEG0=FINAL_DSEG() REXB4=0 REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b001 | BASE0=Ar17() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b001 | BASE0=Ar25() SEG0=FINAL_DSEG() REXB4=0 REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b010 | BASE0=Ar18() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b010 | BASE0=Ar26() SEG0=FINAL_DSEG() REXB4=0 REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b011 | BASE0=Ar19() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b011 | BASE0=Ar27() SEG0=FINAL_DSEG() REXB4=0 REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG() REXB4=0 REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b100 | BASE0=Ar20() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b100 | BASE0=Ar28() SEG0=FINAL_DSEG() # FIXME the d/8 for MOD=01_ and d/32 for MOD=10_ case are redundantly # specified in the manuals. I removed them from here, but the d/32 for # MOD=00_ is required as it is unique. # I redunantly specify DISP_WIDTH=8 or DISPWITH=32 for the MOD=01_ and # MOD=10_ cases so that the encoder will pick the right one even though we # accept the displacment at a higher level. REXB4=0 REXB=0 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() enc REXB4=0 REXB=0 SIBBASE=0b101 MOD=0b01 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=8 REXB4=0 REXB=0 SIBBASE=0b101 MOD=0b10 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=32 REXB4=1 REXB=0 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() enc REXB4=1 REXB=0 SIBBASE=0b101 MOD=0b01 | BASE0=Ar21() SEG0=FINAL_SSEG() DISP_WIDTH=8 REXB4=1 REXB=0 SIBBASE=0b101 MOD=0b10 | BASE0=Ar21() SEG0=FINAL_SSEG() DISP_WIDTH=32 REXB4=0 REXB=1 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b101 MOD=0b01 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=8 REXB4=0 REXB=1 SIBBASE=0b101 MOD=0b10 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=32 REXB4=1 REXB=1 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b101 MOD=0b01 | BASE0=Ar29() SEG0=FINAL_DSEG() DISP_WIDTH=8 REXB4=1 REXB=1 SIBBASE=0b101 MOD=0b10 | BASE0=Ar29() SEG0=FINAL_DSEG() DISP_WIDTH=32 REXB4=0 REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b110 | BASE0=Ar22() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b110 | BASE0=Ar30() SEG0=FINAL_DSEG() REXB4=0 REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() REXB4=0 REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() REXB4=1 REXB=0 SIBBASE=0b111 | BASE0=Ar23() SEG0=FINAL_DSEG() REXB4=1 REXB=1 SIBBASE=0b111 | BASE0=Ar31() SEG0=FINAL_DSEG() #FIXME: 2008-10-01 make these in to nops! OVERRIDE_SEG0():: mode16 | mode32 | mode64 | OVERRIDE_SEG1():: mode16 | mode32 | mode64 |