axi-uartlite

Crates.ioaxi-uartlite
lib.rsaxi-uartlite
version0.1.1
created_at2025-11-28 09:41:39.186587+00
updated_at2025-11-28 09:44:56.206908+00
descriptionLogiCORE AXI UART Lite v2.0 driver
homepagehttps://egit.irs.uni-stuttgart.de/rust/axi-uartlite
repositoryhttps://egit.irs.uni-stuttgart.de/rust/axi-uartlite
max_upload_size
id1955018
size53,436
Robin Mueller (robamu)

documentation

README

Crates.io docs.rs ci

AXI UARTLITE driver

This is a native Rust driver for the AMD AXI UART Lite v2.0 IP core.

Core features

  • Basic driver which can be created with a given IP core base address and supports a basic byte-level read and write API.
  • Support for embedded-io and embedded-io-async

Features

If the asynchronous support for the TX side is used, the number of statically provided wakers can be configured using the following features:

  • 1-waker which is the default
  • 2-wakers
  • 4-wakers
  • 8-wakers
  • 16-wakers
  • 32-wakers
Commit count: 0

cargo fmt