bitvec_simd

Crates.iobitvec_simd
lib.rsbitvec_simd
version0.20.5
sourcesrc
created_at2021-12-02 11:25:07.210146
updated_at2022-03-22 01:59:13.013127
descriptionbitvec with SIMD
homepagehttps://github.com/gccfeli/bitvec_simd
repositoryhttps://github.com/gccfeli/bitvec_simd
max_upload_size
id491159
size75,723
GCCFeli (GCCFeli)

documentation

https://docs.rs/bitvec_simd

README

bitvec_simd

GHA Status Latest Version Documentation License Minimum Supported Rust Version

A rust library for bit vector, featuring:

  • SIMD accelerated via wide.
  • Serialize and deserialize via serde.
  • Stack allocation when bit count is small via smallvec.
  • #![no_std] support.
  • Many performance optimisations.

Usage

Add bitvec_simd to Cargo.toml:

[dependencies]
bitvec_simd = "0.20"

If you want serde support, include the feature like this:

[dependencies]
bitvec_simd = { version = "0.20", features = ["serde"] }

If you want to use bitvec_simd in a program that has #![no_std], just drop default features:

[dependencies]
bitvec_simd = { version = "0.20", default-features = false }

Example


let mut bitvec = BitVec::ones(1000); // create a bitvec contains 0 ..= 999
bitvec.set(900, false); // delete 900 from bitvec
bitvec.set(1200, true); // add 1200 to bitvec (and expand bitvec to length 1201)
let bitvec2 = BitVec::ones(1000);

let new_bitvec = bitvec.and_cloned(&bitvec2); // and operation, without consume
let new_bitvec2 = bitvec & bitvec2; // and operation, consume both bitvec

// Operation Supported:
// and, or, xor, not, eq, eq_left

assert_eq!(new_bitvec, new_bitvec2);

Performance

Compared on AMD Ryzen 7 3700X, aginst:

$ cargo bench       

bitvec_simd(this crate) time:   [465.32 ns 468.04 ns 471.35 ns]
Found 7 outliers among 100 measurements (7.00%)
  2 (2.00%) high mild
  5 (5.00%) high severe

bit-vec 0.6             time:   [1.9115 us 1.9129 us 1.9147 us]
                        change: [+0.0742% +0.2796% +0.5452%] (p = 0.01 < 0.05)
                        Change within noise threshold.
Found 4 outliers among 100 measurements (4.00%)
  1 (1.00%) high mild
  3 (3.00%) high severe

bitvec 1.0              time:   [598.79 us 599.30 us 599.99 us]
                        change: [-0.1615% +0.1525% +0.3552%] (p = 0.30 > 0.05)
                        No change in performance detected.
Found 14 outliers among 100 measurements (14.00%)
  1 (1.00%) high mild
  13 (13.00%) high severe

bitvec_simd(this crate) with creation
                        time:   [1.6427 us 1.6455 us 1.6491 us]
Found 2 outliers among 100 measurements (2.00%)
  2 (2.00%) high severe

bit-vec 0.6 with creation
                        time:   [2.4678 us 2.4696 us 2.4716 us]
                        change: [+1.1134% +1.3933% +1.6146%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 4 outliers among 100 measurements (4.00%)
  3 (3.00%) high mild
  1 (1.00%) high severe

bitvec 1.0 with creation
                        time:   [220.12 us 220.81 us 221.71 us]
                        change: [-0.7438% -0.2211% +0.1436%] (p = 0.41 > 0.05)
                        No change in performance detected.
Found 9 outliers among 100 measurements (9.00%)
  5 (5.00%) high mild
  4 (4.00%) high severe

Reference

Some code of this crate is from (https://github.com/horasal/bitvector_simd)

License

This project is licensed under MIT License (LICENSE-MIT).

Commit count: 39

cargo fmt