Crates.io | extract_rust_hdl_interface |
lib.rs | extract_rust_hdl_interface |
version | 0.2.0 |
source | src |
created_at | 2023-03-17 12:31:32.800336 |
updated_at | 2023-06-17 11:22:42.55152 |
description | Extracts the information needed for a rust-hdl module from a verilog module |
homepage | https://github.com/zebreus/bachelor-thesis/tree/master/bambu-macro/extract_rust_hdl_interface |
repository | https://github.com/zebreus/bachelor-thesis |
max_upload_size | |
id | 812665 |
size | 63,094 |
This crate provides a extract_rust_hdl_interface
function that extracts all the info you need to generate a rust-hdl module from a Verilog module.
The function does not actually generate code it just extracts the interface. It is mainly meant be used through the wrap_verilog!
macro.