Crates.io | gsim |
lib.rs | gsim |
version | 1.1.1 |
source | src |
created_at | 2023-11-29 15:53:49.283269 |
updated_at | 2024-04-08 17:31:26.78 |
description | High speed digital logic simulation |
homepage | |
repository | https://github.com/Artentus/gsim |
max_upload_size | |
id | 1053244 |
size | 654,239 |
Gsim is a digital circuit simulation engine optimized for high simulation speed.
use gsim::*;
use std::num::NonZeroU8;
pub fn main() {
let mut builder = SimulatorBuilder::default();
// Add wires and components to the simulation
let wire_width = NonZeroU8::new(1).unwrap();
let input_a = builder.add_wire(wire_width).unwrap();
let input_b = builder.add_wire(wire_width).unwrap();
let output = builder.add_wire(wire_width).unwrap();
// The gate ID is not usefull to us because we don't intend on reading its data
let _gate = builder.add_and_gate(&[input_a, input_b], output).unwrap();
// Create the simulation
let mut sim = builder.build();
// Manually drive the input wires
sim.set_wire_drive(input_a, &LogicState::from_bool(true)).unwrap();
sim.set_wire_drive(input_b, &LogicState::from_bool(false)).unwrap();
// Run the simulation
const MAX_STEPS: u64 = 2;
match sim.run_sim(MAX_STEPS) {
SimulationRunResult::Ok => {}
SimulationRunResult::MaxStepsReached => panic!("simulation did not settle within allowed steps"),
SimulationRunResult::Err(err) => panic!("simulation error: {err:?}"),
}
// Make sure we got the expected result
let output_state = sim.get_wire_state(output).unwrap();
assert!(output_state.eq(&LogicState::from_bool(false), wire_width));
}