Crates.io | imxrt-ral |
lib.rs | imxrt-ral |
version | |
source | src |
created_at | 2020-02-11 05:49:52.480016 |
updated_at | 2024-12-03 00:28:19.119775 |
description | Register access layer for all NXP i.MX RT microcontrollers |
homepage | |
repository | https://github.com/imxrt-rs/imxrt-ral |
max_upload_size | |
id | 207233 |
Cargo.toml error: | TOML parse error at line 27, column 1 | 27 | autolib = false | ^^^^^^^ unknown field `autolib`, expected one of `name`, `version`, `edition`, `authors`, `description`, `readme`, `license`, `repository`, `homepage`, `documentation`, `build`, `resolver`, `links`, `default-run`, `default_dash_run`, `rust-version`, `rust_dash_version`, `rust_version`, `license-file`, `license_dash_file`, `license_file`, `licenseFile`, `license_capital_file`, `forced-target`, `forced_dash_target`, `autobins`, `autotests`, `autoexamples`, `autobenches`, `publish`, `metadata`, `keywords`, `categories`, `exclude`, `include` |
size | 0 |
A Rust register access layer (RAL), and SVD patches for NXP i.MX RT processors.
The imxrt-ral
is a lower-level interface for i.MX RT processor registers with useful macros. The imxrt-ral
is modeled after the stm32ral
crate. It provides direct access to the processor's registers. Use the imxrt-ral
if you'd like to create your own hardware abstraction layer, or a custom driver.
The imxrt-ral
supports these i.MX RT processors:
"imxrt1011"
"imxrt1015"
"imxrt1021"
"imxrt1051"
"imxrt1052"
"imxrt1061"
"imxrt1062"
"imxrt1064"
"imxrt1176_cm4"
"imxrt1176_cm7"
The RAL also requires a feature flag to specify the processor variant. The RAL is on crates.io. The RAL provides the "rt"
feature flag, and the interrupt table definition, that's used by the HAL.
svd2rust
to generate a crate for register access?See here and here. svd2rust
generates a crate that's nearly 1 million lines of Rust code, and it takes a few minutes to compile. On the other hand, the RAL compiles in a few seconds. Additionally, svd2rust
only supports one SVD input, but the RAL auto-generation script accepts multiple SVD inputs, sharing the common peripherals across processor families. This means that we can more easily support all i.MX RT processor variants from a single crate.
For contributions and development guidance, see CONTRIBUTING.md
Licensed under either of
at your option.