netlist
| Crates.io | netlist |
| lib.rs | netlist |
| version | 0.1.15 |
| source | src |
| created_at | 2023-01-02 13:35:44.386502 |
| updated_at | 2023-09-03 02:48:40.33981 |
| description | generic netlist data structure for VLSI design |
| homepage | |
| repository | https://github.com/eda-rs/netlist |
| max_upload_size | |
| id | 749371 |
| size | 50,993 |
Eric (erihsu)
documentation
README
netlist
Low level library-independent data structure for VLSI design
Purpose
netlist is a common structure in VLSI design, especially in logical synthesis, P&R, formal verification, STA.
This crate wants to abstract netlist to a generic style for more common use.
Feature
1. graph-like data structure
2. verilog parser The verilog parser in this crate is a minimal subset of verilog-2001, which can parse structural verilog syntax into netlist.
3. verilog saver Save netlist as verilog.