oombak_rs

Crates.iooombak_rs
lib.rsoombak_rs
version0.1.0
created_at2025-08-16 11:25:10.758772+00
updated_at2025-08-16 11:25:10.758772+00
descriptionProvides two essential structs: `Dut`, which represents a simulation instance of a SystemVerilog design that you can interact with, and `Probe`, which allows you to traverse your design hierarchy and specify active "probe points" (signals you would like to inspect).
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repositoryhttps://github.com/fuad1502/oombak
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id1798329
size70,276
Fuad Ismail (fuad1502)

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cargo fmt