| Crates.io | parsv |
| lib.rs | parsv |
| version | 0.1.0 |
| created_at | 2024-09-12 00:34:40.851036+00 |
| updated_at | 2024-09-12 00:34:40.851036+00 |
| description | Retrieve any subcomponent from a Verilog module. |
| homepage | |
| repository | |
| max_upload_size | |
| id | 1372379 |
| size | 13,456 |
Verilog and SystemVerilog parsing library.