pytv
| Crates.io | pytv |
| lib.rs | pytv |
| version | 0.5.5 |
| created_at | 2024-03-14 15:59:07.955011+00 |
| updated_at | 2024-04-23 05:06:39.981084+00 |
| description | Python Templated Verilog |
| homepage | |
| repository | https://github.com/autohdw/pytv |
| max_upload_size | |
| id | 1173501 |
| size | 84,849 |
Teddy van Jerry (Teddy-van-Jerry)
documentation
README
PyTV
Python Templated Verilog
Package
The package pytv is available on crates.io.
Documentation is available on docs.rs.
To use the package in a Rust project, run
cargo add pytv
If you want to install the pytv binary, run
cargo install pytv
Features
Python Template
This is the basic feature of this package.
//! a = 1 + 2; # Python inline
assign wire_`a` = wire_b; // Verilog with variable/expression substitute
/*!
b = a ** 2; # Python block
*/
The magic comment string can be configured (! as default).
Instantiation
The crate feature inst is enabled by default.
YAML contents between <INST> and </INST> are used to provide instantiation information.
Related Auto Generator Projects
- FLAMES: template-based C++ library for Vitis HLS [website] [GitHub] [paper at IEEE] [paper PDF]
- AHDW: a DSL, the predecessor of this project [paper at IEEE] [paper PDF]