Crates.io | qingke |
lib.rs | qingke |
version | 0.2.0 |
source | src |
created_at | 2023-02-19 16:30:40.354285 |
updated_at | 2024-05-11 11:08:17.414435 |
description | Low level access to WCH's QingKe RISC-V processors |
homepage | https://github.com/ch32-rs/qingke |
repository | https://github.com/ch32-rs/qingke |
max_upload_size | |
id | 789146 |
size | 27,760 |
Low level access to WCH's QingKe RISC-V processors.
This crate provides the runtime support for QingKe RISC-V processors.
This provides riscv
/riscv-rt
like functionality, with the following differences:
highcode
handlingriscv-rt
crate#[qingke_rt::entry]
fn main() -> ! {
loop {}
}
// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }
#[qingke_rt::interrupt]
fn UART0() {
// ...
}
#[qingke_rt::highcode]
fn some_highcode_fn() {
// ...
// This fn will be loaded into the highcode(SRAM) section.
// This is required for BLE, recommended for interrupt handles.
}