rtlicious

Nom-based parser for Yosys RTLIL text representation.

Usage:

    use rtlicious;
    let src =
    r#"module \test
    wire $a
    end
    "#;
    let design = rtlicious::parse(src).unwrap();
    assert_eq!(design.modules().len(), 1);
    dbg!({:?}, design);

> Design {
    autoidx: None,
    modules: {
        "test": Module {
            attributes: {},
            parameters: {},
            wires: {
                "a": Wire {
                    width: 1,
                    offset: 0,
                    input: false,
                    output: false,
                    inout: false,
                    upto: false,
                    signed: false,
                    attributes: {},
                },
            },
            memories: {},
            cells: {},
            processes: {},
            connections: [],
        },
    },
}