rvv-asm

Crates.iorvv-asm
lib.rsrvv-asm
version0.2.1
sourcesrc
created_at2022-01-11 08:16:38.730935
updated_at2022-07-28 06:10:19.754167
descriptionProcedure macro to encode RISC-V V extension (rvv) instructions
homepage
repositoryhttps://github.com/TheWaWaR/rvv-encoder
max_upload_size
id512114
size14,429
(joii2020)

documentation

README

Example usage

unsafe {
    rvv_asm::rvv_asm!(
        "vsetvl x5, s3, t6",
        "1: vle256.v v3, (a0), vm",
        "2:",
        "li {lo}, 4",
        lo = out(reg) lo,
    );
}
Commit count: 60

cargo fmt