VLaDOS

(System)Verilog Language -- a Definitively Open Simulator

VLaDOS is a very early (and probably broken) alpha SystemVerilog compiler and simulator. The goals of the project are to:

1. Compile code that adheres to the SystemVerilog LRM
2. Act as a drop-in replacement for most other big-name compilers, such as Synopsys VCS, Mentor Questa, or Cadence Xcelium
3. Remain free and open-source so that anyone can compile and run SystemVerilog code locally on any major computing platform