xilinx-dma
| Crates.io | xilinx-dma |
| lib.rs | xilinx-dma |
| version | 0.0.10 |
| source | src |
| created_at | 2021-08-27 12:01:20.4586 |
| updated_at | 2023-12-04 11:10:44.152284 |
| description | Userspace Xilinx AXI DMA Interface |
| homepage | https://www.futuresdr.org |
| repository | https://github.com/futuresdr/xilinx-dma/ |
| max_upload_size | |
| id | 443059 |
| size | 70,665 |
Bastian Bloessl (bastibl)
documentation
README
Xilinx AXI DMA Userspace Driver
This crates uses udmabuf and a generic
userspace I/O driver (uio_pdrv_genirq) to interface Xilinx AXI DMA
controllers. Please see this blog post
and the example
directory for
further information.
Overview
The project is very much work-in-progress. At the moment, it only supports register mode transfers (i.e., no scatter gather). The crate supports sync and async operation.
Contributions
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the project, shall be licensed as Apache 2.0, without any additional terms or conditions.