xlsynth-g8r
| Crates.io | xlsynth-g8r |
| lib.rs | xlsynth-g8r |
| version | 0.26.0 |
| created_at | 2025-03-19 08:19:28.745724+00 |
| updated_at | 2026-01-19 04:42:51.743684+00 |
| description | XLS IR to gate mapping |
| homepage | https://github.com/xlsynth/xlsynth-crate |
| repository | https://github.com/xlsynth/xlsynth-crate |
| max_upload_size | |
| id | 1597802 |
| size | 1,851,015 |
Chris Leary (cdleary)
documentation
https://docs.rs/xlsynth
README
xlsynth-g8r: gate-level infrastructure
xlsynth-g8r hosts the gate-level side of the xlsynth stack:
aig: core AIG/GateFn representation and structural transforms (fraig, balancing, etc.).aig_serdes: (de)serialization to/from AIGER and a textual gate format.aig_sim: scalar and SIMD gate-level simulators.liberty/liberty_proto: Liberty parsing, indexing, and proto bindings.netlist: Verilog-like gate-level netlist parsing, connectivity, cone traversal, and GV→IR.transforms: local gate-level rewrite passes used by optimization and MCMC logic.
Most functionality is exposed via the xlsynth_g8r library and thin binaries under src/bin/.
Netlist parse benchmark
Run the synthetic netlist-parse microbenchmark with:
cargo bench -p xlsynth-g8r --bench netlist_parse_bench -- --verbose