yaxpeax-avr

Crates.ioyaxpeax-avr
lib.rsyaxpeax-avr
version0.1.0
sourcesrc
created_at2020-04-18 08:01:29.71648
updated_at2021-07-18 04:44:08.935191
descriptionAVR instruction set decoder for yaxpeax
homepage
repositoryhttps://github.com/The6P4C/yaxpeax-avr
max_upload_size
id231424
size48,999
iximeow (iximeow)

documentation

README

yaxpeax-avr

AVR decoders implemented as part of the yaxpeax project. Implements traits provided by yaxpeax-arch.

Known "issues"

  • The brbc and brbs instructions are displayed as their equivalent pseudo-instructions, based on the bit they test: brbc 0, label becomes brsh label. In this case specifically, brcc also exists (and is identical), however brsh will be displayed.
  • Target specification is limited to enabling/disabling support for 16-bit sts and lds instructions (as they can collide with other instructions cores with support for them don't have). Valid instructions (even if they might be unsupported by a core) are never rejected. Bytes which don't resemble an instruction from any instruction set subset are still invalid.
Commit count: 8

cargo fmt